Why to use FPGA Emulation-based Fault Injection?
Why semiconductors are more and more sensitive to atmospheric radiation?
What types of components are targeted by Diafim?
Configuration bits of SRAM-based FPGAs Bits are the most sensitive part to SEU in an FPGA, so why should I check the vulnerability of the logic?

Emulation-based Fault Injection has been introduced as a better solution for reducing the execution time compared to simulation-based fault injection.

Both the increased density of semiconductors and the lower voltages increase the sensitivity to atmospheric radiation

Of course, configuration bits of SRAM-based FPGAs are susceptible to single-event upsets (SEUs) and this is why manufacturers have implemented error detection and correction codes to correct SEUs occurred in LUTs of the FPGA. You have also the choice to use rad hard FPGA components to decreases and reenforce the resistance to SEU.

Nevertheless, configuration bits of SRAM-based FPGAs is only one part of the problem. if you want to have a secure and safe circuit, you cannot avoid testing the vulnerability of your circuit to SEUs and possibly hardening sensitive areas by applying redundant logic techniques such as Triple Modular Redundancy (TMR) for example which is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms to prevent upsets which can generate an error in the output.

All Flip-Flops of your design can be instrumented

Yes, with DiaFim you can choose to apply faults on one FF or on as many FFs you need

DiaFim is very useful to verify vulnerability of digital ASICs and IPS but also any kind of design running on FPGAs

The limit is virtually 4 billion tests per suite of tests!. You can set as many suites per test campaign (on the same design). In practice, the limit is the time required for each test multiplied by the number of tests.

A one day training period is enough to be able to play with the product.

  • Stuck-at-0: A selected net is set to static 0 once the fault is injected.
  • Stuck-at-1: A selected net is set to static 1 once the fault is injected.
  • SEU Fault (Bitflip): Once the fault is injected, the state of the selected net toggles for a single clock cycle only.

Faults duration are by default 1 cycle for bit-flip, till the end of test for stuck-at-0 and  stuck-at-1. However, user can choose any number of cycles either statically (same duration for all the tests of the suite) or dynamically (the platform chooses the actual duration randomly from range(s) of durations).