SAFETY IS OUR TOP PRIORITY
A wider and wider range of ICs are nowadays used in safety-critical applications such as medical, space, automotive, nuclear and avionics.
Temporary malfunction of ICs is often caused by Single Event Upsets (SEUs) also known as soft errors or transient faults. That is why several safety standards require to detect and to mitigate a certain percentage of safety critical SEUs. SEUs usually flip the state of a memory cell, a latch, or a flip-flop, until the state is re-written. For example, the Automotive standard ISO 26262 requires that a certain percentage of safety critical SEUs are detected and mitigated.
This percentage must be at least 90% to 99%, depending on the ASIL (Automotive Safety Integrity Level) of the device. Consequently, there is a tremendous need for the evaluation of the dependability of such complex systems using robust tools and methodology.
By bringing the Diafim product to the market, we provide an answer in terms of tools and methodology in the evaluation of the sensitivity of ICs to SEUs and a capability to the user to quickly inspect all parts of their circuits.
RADIATION EFFECTS AND PHYSICS OF FAILURE ON ICs
Single Events Effects (SEEs) are caused by particles (electron, protons, muons etc.) with energies between 0.1 and 20 GeV. By generating electron-hole pairs inside the device, this local ionization creates a pulse of current which can modify the state of a flip flop or a memory cell. This is known as Single Event Upset (SEU). These soft errors can be Single Bit Upset (SBU) or Multiple Bit Upset (MBU) and may cause a fault in the functioning of the device. Considering the increasing reduction of the transistor size, more and more SEE effects appears in electronic devices, then it becomes important to test the hardening of the logic and to assess its resistance to the ionizing particles.
VULNERABILITY ASSESSMENT IS OUR MAIN CONCERN
In circuit-based microprocessors, several portions of the circuit are vulnerable to SEU, 1st and 2nd- level cache memories, state machine etc. and the risk to enter in “dead” states with no exits are important. Getting data on ICs single event upset (SEU) sensitivities are generally obtained from radiation ground testing, but this technique has several limitations in terms of test coverage, costs and reproducibility.
Furthermore, with the radiation tests, it is difficult to see if all the defense mechanisms have been implemented because the events do not necessarily happen at the desired location.
Fault injection tools based on simulation are now on the market and despite their precision, the main drawback remains their low speed which can be a problem if the injection campaign and the circuit are quite large!
Using FPGAs based emulation platform, Diafim provides a solution between radiation ground testing and simulations allowing to quickly obtain a mapping of the sensitivity of your ICs to SEUs by carrying out injection campaigns within the context of the circuit. This technology enables to run several tests campaigns in a very short time and can be seen as a top entry tool reserving simulation only on the most critical parts of the design.
DRAMATICALLY SHORTEN YOUR PROCESS TIME WITH TEST FAULT INJECTION WITHIN OPERATIONAL CONTEXT
Testing your design within FPGA context speed-up tremendously the overall fault injection process reducing checking time by very large factor. The larger is the design the bigger is the ratio compared to simulations. Design under test is typically run at more than 50 M cycles per second.
The speed of execution of the tests allows to considerably increase the number of scenarios and thus increase test coverage.
In addition to that, the association of the signal name with the injector allows very precise targeting of the injection site.